The present invention relates to parallel inverter structures with common DC input and more specifically to an apparatus for reducing circulating currents that result when inverters are linked in parallel.
A typical three phase inverter structure includes six switching devices (e.g., IGBTs) that are arranged between positive and negative DC buses of a rectifier apparatus to form first, second and third switch legs where each leg includes a pair of switches. The first leg includes first and second switches arranged in series, the second leg includes third and fourth switches in series and the third leg includes fifth and sixth switches where nodes between each switch pair are linked to different phases of a three phase load. The above topology is generally referred to as a single inverter structure. By controlling the switching cycles of the six switches the DC voltage across the DC buses is converted into three phase AC voltage that is delivered to the load.
When power requirements beyond the capability of a large single inverter structure are required, one solution has been to arrange single inverter structures in parallel. In this regard, a typical parallel inverter assembly includes two or more single inverter structures that are linked to positive and negative DC buses of a rectifier where the inverter output lines are linked at common coupling points to a load.
As well known in the controls industry, within a parallel inverter structure, during operation, circulating currents typically result due to differences in gate timing signals, switch turn on times, etc.
In addition to differential-mode and common-mode currents that normally flow in a single inverter structure, circulating currents typically flow between the inverters in a parallel assembly where the circulating currents also have common-mode and differential-mode components. The main causes for circulating currents include (1) asynchronous PWM signals (e.g., due to misaligned carrier signals and/or differences in modulating signals); (2) differences in power device characteristics (e.g., differences in switch voltage drops and device switching times; (3) imperfect inverter layouts (e.g., signal delays and mismatched impedances due to unequal cable lengths); and (4) control issues (e.g., inaccurate or unbalanced dead-time compensation, etc.).
Several techniques to synchronize PWM pulse patterns and thereby reduce circulating currents in parallel inverter structures are well known in the art. For instance, one PWM synchronizing hardware solution uses a single controller to generate PWM gating signals for each parallel arranged inverter and related methods to transmit the signals to the individual inverters. Another PWM synchronizing solution includes independent controllers to synchronize phases of PWM carrier signals and operates in a master-slave mode to ensure identical modulating signals. Even with synchronized operation, high frequency circulating currents have been known to persist due to signal delays, differences in switching characteristics of power semi-conductors and inverter dead time.
Where residual circulating currents persist and are appreciable, inter-phase AC reactors have been positioned between output phases of parallel inverters to provide impedance to both high frequency common-mode and differential-mode circulating currents to thereby limit both the magnitude and rate of change of the circulating currents. In these cases inter-phase reactor size depends to a great extent on the degree of mismatch in switching between inverters and additional inverter switching control is required to ensure current sharing among the inverters at low frequencies. Often, despite synchronizing efforts, large reactors have been required to deal with residual circulating currents.
It is also well-known that if inverter PWM switching among parallel linked inverters is synchronized, parallel inverters can be de-rated and operated in parallel without requiring a reactor. Here, parallel inverter layout can be designed such that inherent impedances associated with system linkages (e.g., bus work, cabling, etc.) are sufficient to limit circulating currents to a reasonable level so that reactors and the like are not required. In general de-rating should be minimized or avoided wherever possible and therefore solutions like this one are typically considered less than optimal.
In addition to hardware PWM synchronizing solutions, some software solutions have been developed. For example, one PWM synchronizing software solution includes detecting circulating current at a PWM frequency using a demodulation operation and using the detected circulating current to adjust the phase of a carrier signal used to drive one of the inverters. This solution has been used to operate two standard adjustable speed drives (ASDs) in parallel where PWM patterns cannot be synchronized using some other method and requires high impedance at the AC output.
In some cases PWM synchronization is not possible due to hardware or controller constraints. In cases where PWM synchronization is not possible, circulating currents in parallel inverter structures have been limited by using choke structures.
One known choke configuration for limiting circulating currents includes DC common-mode chokes between a common DC link and each of at least two parallel inverters, with differential-mode AC output chokes positioned at the output ends of each inverter (i.e., between each inverter output and common AC coupling points). Another known choke configuration for limiting circulating currents includes complex integrated common-mode and differential-mode chokes positioned at the output ends of each parallel linked inverter (i.e., between each inverter output and common AC coupling points). In each of these configurations that include chokes, the AC output common-mode currents are sensed and used to independently control each of the parallel linked inverters in an effort to regulate circulating currents. While these solutions provide acceptable operating results, unfortunately, because the common and differential mode circulating currents tend to be large where inverter switching is not synchronized, large differential-mode and common-mode inductances are required.
Thus, except where inverters are de-rated appreciably, in all known cases where inverters are linked in parallel, some type of choke has been required at the output ends of parallel inverters to limit common mode and/or differential mode circulating currents to acceptable levels. As well known in the industry, chokes for high power inverters tend to be extremely large and heavy, and tend to be very complex to design and build and therefore are, in general, very costly.